High-speed communication systems are used to connect computer users together. Networks allow users to share data and work cooperatively. At a physical level, these networks have cables that connect together user's stations, and these cables are in turn connected together using relays or switches. Traditional electro-mechanical relays are being replaced by solid-state relays and bus switches.
Bus switches are semiconductor integrated circuits (IC's) that use metal-oxide semiconductor (MOS) transistors to make or break the connection. Several switches may be combined on a single silicon die. One such device is made by the assignee and marketed as the PI5C3861 Bus Switch. More background on bus switches can be found in "Parallel Micro-Relay Bus Switch for Computer Network Communication with Reduced Crosstalk and Low On-Resistance using Charge Pumps", assigned to Pericom Semiconductor and Hewlett-Packard Company, U.S. Pat. No. 5,808,502, U.S. Ser. No. 08/622,703. Also see "Bus Switch Having Both P- and N-Channel Transistors for Constant Impedance Using Isolation Circuit for Live-Insertion when Powered Down", U.S. Pat. No. 6,034,553, U.S. Ser. No. 09/004,929, assigned to Pericom Semiconductor.
FIG. 1 shows a prior-art bus switch device. A p-channel transistor is connected in parallel to the n-channel transistor to form a complementary metal-oxide-semiconductor (CMOS) bus switch. FIG. 1 shows p-channel transistor 12 connected in parallel with n-channel transistor 10 to form a CMOS bus switch. An enable signal is applied to the gate of n-channel transistor 10. An inverter generates the inverse of the enable signal, which is applied to the gate of p-channel transistor 12. Thus both transistors 10, 12 are enabled or disabled at the same time.
A CMOS bus switch does not develop a voltage drop across the source and drain terminals, even when reduced power supplies are used. For high signals when n-channel transistor 10 becomes saturated, p-channel transistor 12 is still in the linear region of operation and thus passes a full 3-volt signal across its channel without the threshold-voltage drop experienced by a single n-channel transistor.
As networks improve, nodes may have lower capacitance and are thus more susceptible to noise injection. For example, the output node OUT of FIG. 1 may be an isolated node with low capacitance or tight noise margins that is sensitive to noise when isolated by the bus switch.
Noise may be injected into the OUT node by the bus switch itself. As the bus switch is turning off, the gate of n-channel transistor 10 is driven from high to low. A parasitic capacitance from the gate to the source or drain of n-channel transistor 10 couples charge Q to node OUT. A fractional portion of the voltage swing on the gate I capacitivly coupled to the source/drain node OUT. Especially when node OUT has a low capacitance, the voltage swing coupled across n-channel transistor 10 may be sufficient to cause network problems. Charge coupling can also occur when the transistor channel is turning on, from the gate to the main channel.
Even relatively small voltage swings coupled through transistor 10 can upset high-speed analog communication signals that may be transmitted over node OUT. Transmission could be occurring between two other endpoints on node OUT while the bus switch is isolating the common node COM. This transmission could be disturbed by the closing of the bus switch.
Transmission could be stopped while the bus switch is turned on or off, but this is undesirable. It is better if the network can remain in operation while bus switches dynamically isolate and reconnect segments.
FIG. 2 is a graph showing voltage spikes caused by charge injection as a bus switch isolates and reconnects a network segment. As the input signal VIN 14 to the n-channel gate rises in voltage, negative charge is injected into node OUT by gate-source coupling from transistor 12. This injection causes a negative voltage spike on Vout 16. Eventually, as the bus switch turns on, the n-channel and p-channel transistors start to conduct, allowing the voltage spike to be dissipated.
As the bus switch is turned off, VIN 14 falls in voltage. A positive voltage spike is coupled into Vout 16 from the gate of transistor 12. Since the node OUT is now isolated, the voltage spike can have a longer duration before dissipating.
Voltage spikes can occur on both turn off and turn on of the bus switch. The p-channel transistor can also contribute to charge injection, although the p-channel transistor tends to cancel the charge injected by the n-channel transistor, since the voltage swing on the p-channel transistor is always opposite to the swing on the n-channel transistor. However, the p-channel and n-channel transistors are often of different sizes, having different gate-source capacitances. Also, the timing of the n-channel and p-channel voltage swings may not be matched, causing one transistor or the other to dominate charge injection.
What is desired is a bus switch with low noise injection. It is desired to minimize noise injected by a bus switch as the bus switch is turned on and off. It is desired to cancel injected charge to minimize voltage spikes. More precise timing of bus-switch transistors is desirable.